Energy-performance Tunable Digital Circuits a Dissertation Submitted to the Department of Electrical Engineering and the Committee on Graduate Studies of Stanford University in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy

...................................................................................................................................V ACKNOWLEDGEMENTS .......................................................................................................VII TABLE OF CONTENTS ............................................................................................................ IX LIST OF TABLES .................................................................................................................... XIII LIST OF FIGURES ....................................................................................................................XV CHAPTER 1 INTRODUCTION.............................................................................................1 1.1 MOTIVATION ......................................................................................................................1 1.2 ORGANIZATION ..................................................................................................................3 CHAPTER 2 ADAPTIVE OPTIMIZATION TECHNIQUES.............................................5 2.1 INCREASE YIELD BY ADJUSTING THE SUPPLY......................................................................5 2.2 ADAPTIVE VOLTAGE SCALING ............................................................................................7 2.3 BALANCE IN STATIC AND DYNAMIC ENERGY ......................................................................9 2.4 LEAKAGE REDUCTION TECHNIQUES..................................................................................10 2.4.1 Adaptive body bias .................................................................................................12 2.4.2 Variable-Vth CMOS................................................................................................13 2.4.3 Multi-threshold CMOS...........................................................................................14 2.5 CHANGE THE EFFECTIVE THRESHOLD BY SKEWING SUPPLIES ...........................................16 CHAPTER 3 ADJUSTABLE THRESHOLD LOGIC FAMILY .......................................21 3.1 DYNAMIC LOGIC...............................................................................................................21 3.2 PULSE-MODE LOGIC..........................................................................................................24 3.3 PSEUDO-STATIC LOGIC .....................................................................................................27 3.4 DESIGN OF PSEUDO-STATIC GATES ...................................................................................32 3.4.1 Logical effort..........................................................................................................32 3.4.2 Activity factor.........................................................................................................37 3.4.3 Pseudo-static AND gate design example................................................................37 3.5 PSEUDO-STATIC TIMING....................................................................................................41